In Charge Trap Transistor (CTT) technologies, N-type high-k metal gate (HKMG) Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) can be used as multi-time programmable memory (MTPM) elements, resulting in a zero-process-adder and zero-mask-adder solution for embedded non-volatile memory applications. Programming can be achieved by electron injection into the high-k dielectric of the N-type MOSFET, with an elevated gate voltage (Vg) and a relatively high drain bias of 1.5V (deep-on state of the N-type MOSFET). The memory element can be erased by applying a negative gate-to-drain voltage and/or a negative gate-to-source voltage with a magnitude more than 2.5V (a deep-OFF state of the N-type MOSFET), such that the injected electrons are released from the high-k dielectric.
However, existing erasure operations using a deep-OFF state of the N-Type MOSFET often lead to a relatively insufficient erasure of memory. For example, the erase operation, or threshold voltage (VTH) recovery, for certain technology nodes is approximately 50-70%, thereby limiting the endurance required for a MTPM to less than 10× program/erase cycles because of the partial erase. Accordingly, the applications of a CTT MTPM are significantly limited. Furthermore, using a deep-OFF state for an erase operation may cause breakdown of the MOSFET. Although process changes such as the integration of floating gate, magnetic, or resistive elements while optimizing the gate-oxide structure may improve the endurance of a device, the integration of such changes to advanced logic technologies is difficult and expensive, because advanced technologies require FIN structures and multiple phase-shift masks. Therefore, there is a strong demand to realize more than 1000× program/erase cycles of CTT MTPM devices without using additional processes and/or masks in advanced logic technologies.